Various techniques for enhancing semiconductor device performance through manipulation of carrier mobility have been investigated in the semiconductor industry. One of the key elements in this class of technology is the manipulation of stress in the channel of transistor devices by employing lattice mismatched materials in source/drain regions. Such lattice mismatched materials may be advantageously employed to generate stress on a semiconductor device, for example, by applying biaxial stress or uniaxial stress in a channel of a metal-oxide-semiconductor field effect transistor (MOSFET) to improve performance, for example, by increasing the on-current.
One method of providing stress to the channel of a semiconductor device is formation of embedded lattice mismatched semiconductor material portions such as SiGe portions embedded in source and drain regions of a field effect transistor. While embedded lattice mismatched semiconductor material portions are effective sources of mechanical stress on the channel of a field effect transistor, currently known methods of forming such embedded lattice mismatched semiconductor material portions employ filling of trenches having substantially vertical sidewalls in source and drain regions. Because the sidewalls of the trenches are substantially vertical, use of in-situ doped epitaxy to form embedded lattice mismatched semiconductor material portions is impractical due to the outdiffusion of dopants from the embedded regions into the body portion of the transistor and consequent punch-through between the source and the drain.
Further, the upper surfaces of embedded lattice mismatched semiconductor material portions in prior art structures are not self-aligned to the channel of the transistor. Consequently, minor variations in the location of the upper surfaces of the embedded lattice mismatched semiconductor material portions can result in variations in the overlap capacitance and the switching speed of the transistor.